`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:14:24 03/15/2022 
// Design Name: 
// Module Name:    keypad 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module keypad(input        CLK      ,
		 input  [3:0] ROW , 
		 output [3:0] COL ,
		 output [3:0] DATA

    );
	 reg [3:0]Data =4'hf;
	 assign DATA = Data;
	 
	 reg[3:0]col=4'b1110;
	 assign COL = col;
	 always @(posedge CLK)begin
		col <={col[2:0],col[3]};
		
		case( COL )
        4'b1110 :
          case( ROW )
	    4'b1110 : begin Data <= 4'h1; end
	    4'b1101 : begin Data <= 4'h4; end
	    4'b1011 : begin Data <= 4'h7; end
	    4'b0111 : begin Data <= 4'h0; end
          endcase
        4'b1101 :
          case( ROW )
	    4'b1110 : begin Data <= 4'h2; end
	    4'b1101 : begin Data <= 4'h5; end
	    4'b1011 : begin Data <= 4'h8; end
	    4'b0111 : begin Data <= 4'hf; end
          endcase
			4'b1011 :
          case( ROW )
	    4'b1110 : begin Data <= 4'h3; end
	    4'b1101 : begin Data <= 4'h6; end
	    4'b1011 : begin Data <= 4'h9; end
	    4'b0111 : begin Data <= 4'he; end
          endcase
			4'b0111 :
          case( ROW )
	    4'b1110 : begin Data <= 4'ha; end
	    4'b1101 : begin Data <= 4'hb; end
	    4'b1011 : begin Data <= 4'hc; end
	    4'b0111 : begin Data <= 4'hd; end
          endcase
		endcase
	 end


endmodule
